PhD Thesis on Platinum Atomic Layer Deposition: Surface Reactions and Nanopatterning by A.J.M. Mackus (TU/e)

Atomic layer deposition of platinum : from surface reactions to nanopatterning Citation for published version (APA): Mackus, A. Atomic layer deposition of platinum : from surface reactions to nanopatterning. Technische Universiteit Eindhoven.6100/IR754694 Document status and date: Published: 01/01/2013 Document Version: Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record.

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• Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please follow below link for the End User Agreement: www.nl/taverne Take down policy If you believe that this document breaches copyright please contact us at: openaccess@tue.nl providing details and we will investigate your claim. 2022 Atomic Layer Deposition of Platinum from surface reactions to nanopatterning PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Eindhoven, op gezag van de rector magnificus, prof.

van Duijn, voor een commissie aangewezen door het College voor Promoties in het openbaar te verdedigen op maandag 10 juni 2013 om 16.00 uur door Adriaan Jacobus Martinus Mackus geboren te Weert Dit proefschrift is goedgekeurd door de promotor: prof. Kessels Copromotor: dr. Bol This thesis is part of NanoNextNL, a micro and nanotechnology innovation programme of the Dutch Government and 130 partners from academia and industry. More informa- tion on www.

Printed and bound by Printservice Technische Universiteit Eindhoven. Cover design by Nick Meeuws, Orange Vormgevers. A catalogue record is available from the Eindhoven University of Technology Library. ISBN: 978-90-386-3384-8 i Preface This thesis deals with atomic layer deposition (ALD) of platinum and with the develop- ment of a novel nanopatterning approach based on ALD.

The work was carried out in the research group ”Plasma and Materials Processing” (PMP) at the Department of Applied Physics of the Eindhoven University of Technology. The group has a background in the science and technology of plasmas and thin films, and has obtained extensive expertise in the field of (plasma-assisted) ALD in the last decade. The work on nanopatterning was part of a close collaboration between PMP and the company FEI Electron Optics. FEI has contributed to this project with their expertise in charged particle beam processing.

The PhD project has been financially supported by NanoNextNL, a nanotechnology pro- gram of the Dutch government, and by FEI. In the NanoNextNL program, this project is part of the subprogram on ”Nanopatterning”. The results presented in the chapter about carbon nanotube field effect transistor (CNTFET) fabrication were partly obtained during an internship (summer 2012) in the group of Prof. Zhihong Chen at the Birck Nanotechnology Center of Purdue University.

Adrie Mackus Eindhoven, February 2013 iii CONTENTS Chapter 1 Introduction 1 Chapter 2 The use of ALD in advanced nanopatterning 19 Chapter 3 Catalytic combustion and dehydrogenation reactions during 53 ALD of platinum A. 24, 1752 (2012) Chapter 4 Influence of oxygen exposure on the nucleation of platinum 85 ALD: consequences for film growth, nanopatterning, and nanoparticle synthesis A. Kessels, accepted for publication in Chem. Chapter 5 Room-temperature ALD of platinum 103 A.

Kessels, accepted for publication in Chem. Chapter 6 Local deposition of high-purity Pt nanostructures by combin- 121 ing EBID and ALD A. van de Sanden, and W. 107, 116102 (2010) Chapter 7 Nanopatterning by direct-write ALD 131 A.

Kessels, Nanoscale 4, 4477 (2012) Chapter 8 Direct-write ALD of high-quality Pt nanostructures: Selec- 143 tive ALD growth and EBID seed layer requirements A. Kessels, accepted for publication in J. iv Chapter 9 Fabrication of carbon nanotube field effect transistors using 171 direct-write ALD Chapter 10 General conclusions and outlook 193 Summary 199 List of publications related to this work 201 Dankwoord/Acknowledgments 203 Curriculum vitae 205 Chapter 1 Introduction 1.1 Nanomanufacturing In today’s information age, the fast development of computers, mobile phones, tablets, and other electronic devices has an immense effect on the society. This advancement is being driven mostly by the microelectronics industry, which consistently has been delivering faster and smaller computer-chips during the last few decades.

Much of this progress results from following Moore’s law; an economic law and nowadays a “roadmap” that describes that the number of transistors on an integrated circuit should double every 18 to 24 months to maintain continuous device improvement [1]. The tran- sistor, basically an electrical switch (See Fig.1a), is a fundamental building block of which over a billion are typically present in every modern electronic device.1b illustrates the development of transistors in integrated circuits during the past 50 years. During the first four decades after the invention of the integrated circuit in 1958, the performance of a circuit was predominantly improved by down-scaling the dimensions of the transistor [2]. When scaled down, transistors switch faster and con- sume less energy.

The scaling also lowers the price per transistor and allows for the fabrication of more complex circuits containing more transistors. The dimensions of the structures and layers of which the transistor currently consists are at the nanometer scale. In this size regime, the properties of the materials involved deviate from their bulk be- havior. For this and other reasons, it becomes inevitable to implement new materials and to fundamentally change device architectures.

At the 45 nm node in 2007, a hafnium- 2 (a) Gate dielectric Gate Source Drain Channel Substrate (b) 1958 2005 2007 2011 201? 202? 65 nm 45 nm 22 nm Integrated circuit SiO 2 / poly-Si High-k dielectric Tri-gate III - V / Ge CNTFET: dielectric Metal gate architecture channel SWCNT channel Scaling Introduction of new materials New transistor architectures (3D) Figure 1. A MOSFET consists of a semiconducting channel of Si connected to two contacts: a source and a drain. In addition, there is a third contact, the gate, that is separated from the channel by a thin dielectric layer (made traditionally of SiO2 but currently in most cases of HfO2 ). The current in the channel can be controlled by apply- ing a voltage between the gate and the source.

The gate voltage can therefore be used to swith the current between the source and the drain on or off. (b) Overview illustrating the development of the transistor in integrated circuits during the past five decades. Transis- tors were mainly scaled down in size during the first four decades after the invention of the integrated circuit. In recent years, new materials and drastic changes to the architec- ture were implemented.

The next step might be the introdution of new materials for the transistor channel. (Based on images from www.) based oxide deposited by atomic layer deposition (ALD) has been introduced as the gate dielectric [3]. ALD is a thin film deposition technique that allows for the depostion of material in layer-by-layer fashion and has therefore control of the film thickness at the atomic level. The introduction of the hafnium-based oxide layer was necessary in order to minimize the leakage current that plagued the conventional SiO2 gate dielectric when being scaled down to the nanometer level.

In the lastest technology generation of 22 nm, Chapter 1 3 Intel introduced the Tri-Grate (also known as FinFet) architecture, in which the gate is wrapped around the channel in a three-dimensional structure [4]. The wrap-around ar- chitecture improves the coupling between the gate and the channel, and thereby reduces short-channel effects. ALD plays an important role in the nanomanufacturing of this three-dimensional architecture, because the dielectric layer needs to be deposited around the channel with an excellent step coverage [5]. The next fundamental change may be to implement new materials with higher charge carrier mobilities for the transistor chan- nel; first III-V and Ge semiconductors and subsequently nanowires, carbon nanotubes, or graphene [6].

With the implementation of these new materials, the microelectronics industry has reached the stage at which scientific breakthroughs reported in nanoscience need to be converted into nanotechnology. In the last 20 years, many promising architectures for future nanoelectronic devices have been proposed. Their implementation in technology is currently limited due to a lack of reliable nanomanufacturing techniques [7]. A good example is the carbon nanotube field-effect transistor (CNTFET), i.

the transistor archi- tecture in which the silicon channel is replaced by a semiconducting carbon nanotube [8]. Many studies in nanoscience literature demonstrate, for a handful of devices, that CNT- FETs can outperform conventional transistors. However, integrated circuits containing CNTFETs cannot be realized while nanomanufacturing techniques are lacking for the synthesis and wiring of billions of transistors on the nanometer scale [9]. The Interna- tional Technology Roadmap for Semiconductors (ITRS) lists the following challenges for CNTFET fabrication: (i) the carbon nanotubes need to be grown with control of the band gap energy; (ii) the carbon nanotubes need to be positioned at specific locations; (iii) control of carrier type and concentration is required; (iv) a reliable method for gate dielectric deposition needs to be developed; (v) and electrical contacts with a low contact resistance are required [6].

The use of carbon nanotubes or graphene in future carbon nanoelectronics leads to new requirements for the various processing steps in integrated circuit manufacturing. As illustrated in Fig.2, conventional top-down∗ approaches involve the patterning of a resist film and subsequent etching or lift-off. It has been reported that it is extremely dif- ficult to remove resist layers from the surface of carbon-based materials [10, 11], and the resist residue that is left behind affects the performance of the device [12, 13]. Moreover, the chemicals used in etching or lift-off may damage or dope the sensitive surfaces of ∗ In nanomanufacturing, the term top-down describes techniques that start with a large piece of material that is structured by removing material using for example etching.

On the other hand, bottom-up methods are based on the building of nanostructures in a atom-by-atom or molecule-by-molecule fashion. 4 (a) Trial and error (b) Top-down (c) Bottom-up Light exposure Resist film (a) (b) (c) © JPvD Metallization + lift-off Resist residue ©JPvD Nanotube Drain Source Drain Gate Gate dielectric SiO 2 Source Si - back gate SiO2 ©JPvD Figure 1.2: (a) The first CNTFET device reported by Tans et al. The device was fab- ricated by dispersion of carbon nanotubes on a substrate with pre-patterned Au contacts. The Au lines serve as source and drain contacts, the Si substrate as the back gate with a SiO2 layer as the gate dielectric, and the carbon nanotube as the channel.

(b) The con- ventional top-down approach relying on the patterning of a resist layer by lithography, metallization, and lift-off. Resist residue is left behind and contact delamination during lift-off lowers the device yield. (c) Ideally, the device is fabricated using a bottom-up approach in which the contacts are built atom-by-atom only at the targeted location. carbon nanotubes and graphene [13, 14].

These compatibility issues can be overcome by using bottom-up methods in which the structures are created directly at their nanoscale dimensions.